1. Field of the Invention
The present invention relates to a frequency synthesizing circuit, and particularly to a frequency synthesizer which has a low frequency reference signal, a high frequency output, and a high multiple for frequency synthesizing.
2. Description of the Prior Art
Phase-Locked Loop (PLL) is a technique usually used in a frequency synthesizing circuit, as shown in FIG. 1. The basic framework thereof includes a phase-frequency detector (PFD) 14, a charge pump loop filter (CPF) 16, a voltage control oscillator (VCO) 18 and a divider 20. Through the function of the PFD, the output frequency of the VCO can be adjusted accordingly. When the loop is phase locked, the output frequency (fvco) of the VCO and the frequency (fref) of the reference signal will satisfy the formula of fvco=N×fref, wherein N is a coefficient of the divider.
For an application of a high frequency generator (>100 MHz) with a low reference frequency (<100 kHz), such as in a receiver of a video transmission system, a high frequency clock generated from a screen horizontal synchronous signal (HSYNC) is required for an analog to digital converter. In a traditional PLL, a high-ratio divider (N) is required for frequency multiplication. But it often accumulates an extremely large amount of phase errors. In addition, for a low frequency reference signal, the PLL loop bandwidth should be narrowed down which may result in higher phase noise introduced by VCO.
Thus it can be seen, the prior art described above still has some defects, is not a good design, however, and is urgently to be improved.
Because of the technical defects of described above, the applicant keeps on carving unflaggingly to develop the frequency synthesizing circuit through wholehearted experience and research.